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Data Sheet
I DD Specifications AND CONDITIONS
(0°C ≤ T A ≤ + 70°C; V DDQ = +2.5V ± 0.2V, V DD = +2.5V ± 0.2V) see Note 1 on Page 9
Rev.1.1
09.06.2010
Parameter
& Test Condition
OPERATING CURRENT *) : One device bank; Active-
Precharge;
Symb.
I DDO
3200-3033
320
max.
2700-2533
260
Unit
mA
t RC = t RC (Min); t CK = t CK (Min); DQ, DM and DQS inputs
changing
once per clock cycle; Address and control inputs
changing once every two clock cycles
OPERATING CURRENT : *)
One device bank; Active-Read-Precharge;
I DD1
360
320
mA
Burst = 2; t RC = t RC (Min);
t CK = t CK (Min);I OUT = 0mA;
Address and control inputs changing once per clock
cycle
PRECHARGE POWER-DOWN STANDBY CURRENT:
All device banks idle;
I DD2P
20
20
mA
Power-down mode;
t CK = t CK (Min); CKE = (LOW)
IDLE STANDBY CURRENT: CS# = HIGH; All device
banks idle;
I DD2F
92
92
mA
t CK = t CK (Min); CKE= HIGH; Address and other control
inputs changing once per clock cycle.
V IN = V REF for DQ, DQS, and DM
ACTIVE POWER-DOWN STANDBY CURRENT: One
device bank active; Power-down mode; t CK = t CK
I DD3P
80
60
mA
(Min);CKE = LOW
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE =
HIGH; One device bank; Active-Precharge; t RC = t RAS
I DD3N
160
160
mA
(Max); t CK = t CK (Min); DQ, DM and DQS inputs
changing twice per clock cycle; Address and other
control inputs changing once per clock cycle
OPERATING CURRENT:
Burst = 2; Reads; Continous burst; One bank active;
I DD4R
540
380
mA
Address and control inputs changing once per clock
cycle; t CK = t CK (Min);
I OUT = 0mA
OPERATING CURRENT: Burst = 2; Writes; Continuous
burst; One device bank active; Address and control
I DD4W
540
440
mA
inputs changing once per clock cycle; t CK = t CK (Min);
DQ, DM, and DQS inputs changing twice per clock
cycle
AUTO REFRESH CURRENT
t RC = t RC (Min)
I DD5
540
400
mA
t RC = 7.8125μs
SELF REFRESH CURRENT: CKE ≤ 0.2V
OPERATING CURRENT *) : Four device bank interleaving
READs (BL =4) with auto precharge, t RC = t RC (Min);
I DD5A
I DD6
I DD7
20
12
1040
20
12
960
mA
mA
mA
t CK = t CK (Min); Address and control inputs change only during
Active READ, or WRITE commands
*) Value calculated as one module rank in this operating condition, and all other module ranks in IDD2P (CKE LOW)
mode.
Swissbit Germany AG
Wolfener Stra?e 36
D-12681 Berlin
Fon: +49 (0) 30 93 69 54 - 0
Fax: +49 (0) 30 93 69 54 - 55
www.swissbit.com
eMail: info@swissbit.com
Page 7
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